1. Field of the Invention
This invention relates to an improved metal-to-metal antifuse and a method of making a metal-to-metal antifuse which yields an antifuse having a more predictable break down voltage than available in prior art antifuses.
2. The Prior Art
Field Programmable Gate Arrays (FPGAs) and other modern user programmable semiconductor devices comprise antifuses as programmable elements to effect user programmability of the functions and operation of such devices. Antifuses are generally devices which comprise a pair of conductive layers sandwiched about an insulating antifuse layer. Application of a voltage in excess of the "programming" or breakdown voltage of the antifuse across the conductive layers causes a conductive filament or "via link" to form in the antifuse layer between the two conductive layers, effectively shorting the two conductive layers together and "programming" the antifuse to an "on-state." An unprogrammed antifuse has no conductive filament connecting the two conductive layers, hence it is in the "off-state."
Antifuse conductive layers have been fabricated from a number of different conductive layer materials as well as a number of different insulating antifuse materials. Antifuse on-state resistances vary from a few ohms to a few hundred ohms, depending upon the materials and structure used, while the off-state resistances range to a few gigaohms. Programming voltages range from a few volts to about 20 volts.
The programming voltage of an antifuse is essentially a function of the thickness of the antifuse layer. The thinner the layer, the less the programming voltage, the thicker the layer, the higher the programming voltage. Any unpredictability in the thickness of the antifuse layer resulting from the processes used to fabricate the antifuse will translate into an uncertainty in the programming voltage for the fuse as well as an uncertainty in the operating voltages which may safely be used without inadvertently programming the antifuse.
Because antifuses are used to program the functions and operation of FPGAs and other applications of user programmable semiconductor devices, the failure of an antifuse, either due to inadvertent programming or inability to program at the predicted programming voltage can render an entire device inoperative and defective. Others have tried to improve the yield and predictability of antifuses, however, the devices of the prior art remain somewhat unreliable when built to be programmed and operate at the lower voltages present in today's semiconductors. This is in large part due to the fact that most metal-to-metal antifuses, which are favored in CMOS compatible processes, are made by opening a via in the dielectric layer and then applying the antifuse layer over and in the via. The result is a layer of varying thickness which may form cusps in the non-square via. For example, U.S. Pat. No. 5,120,679 to Boardman et al. teaches an antifuse structure having oxide spacer elements to cover cusps formed in the amorphous silicon ("a-Si") insulating antifuse layer which is applied to an opening in the dielectric layer. Boardman's device, necessarily, has a relatively unpredictable antifuse layer thickness and he attempts to get around this by shielding all but the central portion of the layer in the middle of the via.
More recently, strap type architectures have become available in the art which allow for a planar antifuse layer, avoiding the problems noted by Boardman et al. In the paper "Field Programmable Gate Array (FPGA) Process Design For Multilevel Metallization Technology" by K. S. Ravindhran et al. presented at the June, 1993 VMIC Conference, the structure disclosed is essentially that set forth in FIG. 1.
Turning to FIG. 1 an antifuse structure 10 similar to that taught by K. S. Ravindhran et al., supra, is shown. A first metallization layer 12 is disposed on an insulating portion of an integrated circuit, such as silicon dioxide. Metallization layer 12 may comprise, for example, TiW. A first amorphous silicon ("a-Si") layer 14 is disposed over TiW layer 12. A dielectric layer, such as a CVD oxide layer 16 is disposed over first a-Si layer 14. A via 18 is opened in oxide layer 16 with an etch gas. The etch process is stopped after the via extends all of the way through oxide layer 16 and partially into first a-Si layer 14 in the region denoted with reference numeral 20. A second metallization layer 22 is disposed over via 18. Second metallization layer 22 may comprise a first layer 24 of TiW and a second layer 26 of aluminum.
Unfortunately, the antifuse layer is reached by etching an opening in a CVD oxide dielectric layer. Because the antifuse layer can also be etched by the gases used to etch the dielectric layer, an unpredictable amount of antifuse is also etched away during the process resulting in a somewhat unpredictable thickness for the antifuse layer and a corresponding unpredictable programming voltage. As operating and programming voltages drop to accommodate lower powered devices, the problems presented by this unpredictability grow large. Accordingly, there is a need for an improved antifuse structure and method for making the same which provides a highly predictable and repeatable programming voltage.